Replacement for the gate array in the 1541


The floppy disk drive VC1541 from Commodore, was subjected to some modifications again and again in the course of the time. Mostly these were savings for cost reasons.

In the 80s TTL chips of the 74 series recently cost more than today. Where today most chips from this series cost on average 0.50 euros, or imported from China even some only a fraction of that, so these cost much more at that time. Rarer copies also gladly converted 5, – Euro per piece.

In addition, there were also delivery problems with these ICs from time to time. To avoid these problems, Commodore developed an own chip, which integrates a whole handful of these TTL chips in one package. This is how the MOS 325572-01 was created.

The gate array on slot UC1

This allowed Commodore to save not only costs but also space, which of course saved further costs for the board.

Unfortunately, this chip also tends to break. And replacements are only available in the form of used chips. However, these are sometimes more expensive individually than a used and functional 1541.

So the idea is obvious to copy the chip somehow or to build it.

What’s in this IC?

What is in the gate array can be estimated quite well. Because in the end, everything that was still present on the “longboard” TTL chips, and the “shortboard” no longer, is just in the gate array.

And there are also corresponding schematics of the longboard in the Commodore service manual.

In the said document, on the one hand, there is a functional diagram:

Internal structure of the gate array

This already gives you a rough overview of what is in UC1 and what function it performs. At the bottom right, for example, you can see the control for the drive motor and stepper motor of the read/write head, etc.

This would already be sufficient to be able to reproduce the logic. However, Commodore makes it easy, because it also includes the schematic how this logic was built on the old “longboard”.



So basically you just need to rebuild exactly the “missing” part on the “shortboards”.

Replica in TTL

And it sounds more difficult than it was. Because you really only need to rebuild the circuit 1:1 and then just distribute the corresponding signal lines to the 40 pins of the UC1.

To try the whole thing out, but also to make measurements easier, I rebuilt the MOS 325572-01 in single TTL chips.

Replica in TTL

The circuit board stands slightly above…

TTL grave seen from the side

A total of 15 TTL devices were needed. Two of them are only needed for one gate each. On the longboard free gates of existing chips were simply used. This did not work here of course. Of course I could have built the whole thing in SMD, but it would not have been much smaller.

But it was a nice fun and you learn quite a bit about how this circuit works.

Now the whole thing in nice

The next goal was to reproduce the whole thing in a CPLD or FPGA in a space-saving way. Most of today’s CPLDs or FPGAs are only designed for 3.3V or less. Of course you could put level shifters in between. But this would need more space.

But there are still a few CPLDs and FPGAs that are at least 5V tolerant. This means that they work with 3.3V but accept 5V at the inputs without problems. But at the outputs there is still only a “Low Voltage TTL level” with 3.3V. But this is no problem, because with TTL everything over 2V is a HIGH level.

Lattice, Altera and Xilinx no longer officially have such chips in their program. But since these chips are very popular, they are still available in large quantities and will be for some years.

I chose the Xilinx XC95144XL for the first tests. Actually totally oversized, I have plenty of it in stock. And this chip costs just under one euro in China. It probably doesn’t get much cheaper than that.

First experiments

As nice as the simulations in the individual tools are, I’ve always found that the simulations don’t always help, especially in combination with old hardware. What works perfectly in simulations, has its weaknesses here and there in reality. And this is especially true when it comes to almost 40-year-old technology.

So I only used the simulations where there was no outside contact, and otherwise just “simulated” the whole thing on the live model and a logic analyzer.

Certainly not the preferred way, which one learns in trainings, but in these trainings one also does not meet so old hardware, which none of the simulations can really represent. TTL devices are partially mapped as such, but only as a perfect model. A component, which is 40 years old and perhaps has already had thousands of operating hours, stupidly does not always behave like the perfect model.

So I took one of my self-built experimental boards, and started to recreate the circuit in VHDL.

Experiment board with XC95144XL

Setup with the first prototypes

I have divided the whole thing into individual function blocks. For example, I have chosen the motor control, which works independently from the rest of the gate array.

For this I took the TTL version from above, took out the corresponding ICs and replaced them with single connections of the experimental board.

Experimental board connected to 1541

So I was able to do wonderful tests on the living object, or look for errors. Mostly it was timing problems, when something didn’t work again.

Here is a good example:

Fault analysis

In the bottom row you can see the internal clock signal of the CPLD. At the top you can see an external signal. Actually both should run synchronously. In the simulation this is the case. But the circuit in reality does not.

The middle signals are all triggered by the lower clock signal at rising edge and fit internally as well. Only then not to external outside world.

These are problems that you encounter again and again, and that’s why I left the simulations at some point and only measured directly. This was faster and easier for me.

Some chaos at the workplace in the meantime

In between, it looked a bit chaotic due to all the wires, strings and test leads. But it progressed very fast. However, the wire jam on the experimental board became so large that it happened again and again that connections were interrupted.

So I decided to make a cut here, and move the stand out to a new prototype board.

The 2nd prototype

I swapped out everything that was already finished into the CPLD and still provided the rest as TTL. So the old wire connections were done for now and there was room for many colorful new wires again 🙂

Only two ICs left

On the picture you can see how meanwhile almost everything has already been implemented in the CPLD. The contacts I bent up on the flip flop belong to one of the two flip flops in the 74LS74. This one belonged to another function block and was already implemented. I could not remove the chip completely, because the other FF was still needed.

In between I tested the basic floppy functions by formatting floppies, creating files, deleting files, copying files and even copying whole floppies.

Nearly done…

And now the last two ICs are gone and the CPLD has completely taken over.

CPLD replacement for UC1

No TTL component is used anymore, the sockets are all empty.

I have now cleaned up the VHDL code, deleted temporary assignments again, streamlined the whole thing and also commented it.

Now only the circuit board must become nicer. Because on the one hand no one wants to have these wires and on the other hand the board must become smaller.

If you look at the summary after “compiling” the code, you can see that the XC95144XL used here is much too oversized.

Screenshot of the Xilinx development IDE

A “small” XC9572XL is also completely sufficient here. And from the number of I/Os needed even the very small version in TQFP with 44 pins. It would have fit almost even into the XC9536XL. Unfortunately I needed 3 macro cells more.

However, since I’m still at the beginning as far as VHDL is concerned, I might take on the project again later. I think that I will then be so far fit in VHDL that I could certainly still make some optimizations here and there. Then the whole thing could certainly fit into an XC9536XL, even if this does not really make a difference in price.

And this would fit quite easily on such a small board, which would also be no larger than the old chip.


The VHDL code is ready, the whole thing so far also tested, now it is time to bring the whole thing to the conclusion. For this it needs a practical small circuit board.

There is not much circuitry effort here. The Xilinx XC9572XL works internally with 3.3V. This requires a small voltage converter that converts the 5V supplied by the floppy drive to 3.3V and a few blocking capacitors for the CPLD. That was it then already.

In the 3D model, the finished board looks like this.

Seen from above

So that the optics is a little more attractive, I have left the upper side free. So the whole thing still comes closest to an IC. You could perhaps embed the whole thing in black casting resin to complete the look.

The actual circuitry sits on the bottom.

Bottom side of the board

As you can see, the selected CPLD fits wonderfully. On the right you can see the voltage transformer.

Later the CPLD will be replaced by the version with only 44 pins. Unfortunately I didn’t get any others on the fast way, therefore the 64 PIN version.

This is what the real version will look like. Once from above:

EasyGate1541 from above

And once the bottom side:

EasyGate1541 from below

As you can see, the effort is not great at all. The LEDs are more of a gag. There were still I/Os free (referring to the 44 PIN version), so I decided to use them somehow.

Therefore I have installed a clock controller. This shows the presence of the incoming clock signal. For this I have divided the clock accordingly, so that the LED flashes. So you can at least determine whether the clock is present, which is supplied by the UD5.

Further I have installed a motor indicator, which shows whether the motor is in operation. And last but not least I added a power LED, which shows if the voltage converter is working, and a write LED. This LED lights up or blinks when the diskette is accessed for writing.

I had used LEDs here for the first time, which are installed from behind. As I find, a nice gag.

When installed in a 1541, the whole thing looks like this:

EasyGate1541 in installed condition

The circuit diagram is not really exciting:

Circuit diagram of the EasyGate1541

As you can see, there is not really much in the board. The LEDs could also be left out. But somehow I found them so nice as a nice gag that I left them.

This is still the version for the 64Pin version of the XC9572XL. Therefore there are still a lot of unused I/Os. But I couldn’t think of anything else to do something useful. In an earlier version I still had LEDs for the direction of the read/write head on it. But later I removed them again, because they were simply useless.

You could add white LEDs underneath the chip, if someone should ever make a transparent case for the 1541. Would certainly look quite funny. There would also be enough macro cells for a PWM control, so that you could slowly dim them up and down.

Would be a nice idea for long winter evenings…


And this replacement is mercilessly cheap. The chip costs around 2 euros in China. In Germany, it’s around 3-4 euros. The circuit board itself costs the equivalent of one euro, with shipping costs from China. And the “chicken feed” with voltage converter is in the cent range. The LEDs are with nearly 1,50 Euro almost the most expensive part. Whereby these could also be omitted.

The bottom line is that the board costs just under 5 euros. If you make a few dozen of them, it would be more like 3 euros or less.

If you compare the price of used original gate arrays from eBay, this effort was more than worth it. I have not included the development effort for the code. But if someone does this as a hobby, you can not include such costs anyway.

On the net I had found another alternative version with the name “GandALF”. But it has an additional 74LS74 (flip flop) on it. I don’t know the code, but I could imagine what this is for. There was probably tried not to reproduce the logic of the gate array, but to convert the chips 1:1 into code. And Commodore “abused” a flip flop in an interesting way. If you try to use a flip flop in a classical way (maybe the usual code snippets from the internet), this won’t work, because it can’t be synthesized like this…

But it also costs many times more than my solution.

Addendum (2020-12-31) and download

I have also now published this project on GitHub. If you want to rebuild the project, you are welcome to do so. Everything you need is on my GitHub account:

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